Texas Instruments SN74AS161N Handleiding

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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276A – DECEMBER 1994 – REVISED JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Internal Look-Ahead Circuitry for Fast

Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages, Ceramic Chip Carriers (FK),

Standard Plastic (N) and Ceramic (J) DIPs

description

These synchronous, presettable, 4-bit decade

and binary counters feature an internal carry

look-ahead circuitry for application in high-speed

counting designs. The SN54ALS162B is a 4-bit

decade counter. The ’ALS161B, ’ALS163B,

’AS161, and ’AS163 devices are 4-bit binary

counters. Synchronous operation is provided by

having all flip-flops clocked simultaneously so that

the outputs change coincidentally with each other

when instructed by the count-enable (ENP, ENT)

inputs and internal gating. This mode of operation

eliminates the output counting spikes normally

associated with asynchronous (ripple-clock)

counters. A buffered clock (CLK) input triggers the

four ip-ops on the rising (positive-going) edge of

the clock input waveform.

These counters are fully programmable; they can

be preset to any number between 0 and 9 or 15.

Because presetting is synchronous, setting up a

low level at the load (LOAD) input disables the

counter and causes the outputs to agree with the

setup data after the next clock pulse, regardless

of the levels of the enable inputs.

The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input

sets all four of the ip-op outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear

function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets

all four of the ip-op outputs low after the next clock pulse, regardless of the levels of the enable inputs. This

synchronous clear allows the count length to be modied easily by decoding the Q outputs for the maximum

count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear

the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this

function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,

PRODUCTION DATA information is current as of publication date.

Products conform to specications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54ALS161B, SN54ALS162B, SN54ALS163B,

SN54AS161, SN54AS163 . . . J PACKAGE

SN74ALS161B, SN74AS161,

SN74AS163 . . . D OR N PACKAGE

SN74ALS163B . . . D, DB, OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

SN54ALS161B, SN54ALS162B, SN54ALS163B,

SN54AS161, SN54AS163 . . . FK PACKAGE

(TOP VIEW)

CLK

CLR

LOAD

ENT RCO

ENP

GND

NC – No internal connection

VCC

CLR

CLK

ENP

GND

VCC

RCO

ENT

LOAD

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276A – DECEMBER 1994 – REVISED JULY 2000

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

produces a high-level pulse while the count is maximum (9 or 15, with QA high). The high-level overow

ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,

regardless of the level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no eect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for

operation over the full military temperature range of –55°C to 125°C. The SN74ALS161B, SN74ALS163B,

SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.

logic symbols†

CTRDIV10

LOAD

1, 5D

5CT=0

C5/2,3,4+

ENT

RCO

3CT=9

ENP 2

CLK

CLR

SN54ALS162B DECADE COUNTER

WITH SYNCHRONOUS CLEAR

CTRDIV16

LOAD

1, 5D

CT=0

C5/2,3,4+

ENT

RCO

3CT=15

ENP 2

CLK

CLR

[1]

[2]

[4]

[8]

’ ’ALS161B AND AS161 BINARY COUNTERS

WITH DIRECT CLEAR

CTRDIV16

LOAD

1, 5D

5CT=0

C5/2,3,4+

ENT

RCO

3CT=15

ENP 2

CLK

CLR

’ ’ALS163B AND AS163 BINARY COUNTERS

WITH SYNCHRONOUS CLEAR

[1]

[2]

[4]

[8]

[1]

[2]

[4]

[8]

†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, and N packages.

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276A – DECEMBER 1994 – REVISED JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

CLR

LOAD

ENT

ENP

CLK

RCO

SN54ALS162B

11 QD

Pin numbers shown are for the J package.

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74AS161N
Breedte:	19.69 mm
Diepte:	6.6 mm
Hoogte:	4.57 mm
Breedte verpakking:	13.97 mm
Diepte verpakking:	506 mm
Hoogte verpakking:	11.23 mm
Soort:	Logic IC
Type verpakking:	PDIP
Aantal per verpakking:	25 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	0 - 70 °C
Aantal pinnen:	16
Breedte (met pennen):	19.69 mm
Diepte (met pennen):	10.92 mm
Hoogte (met pennen):	8.26 mm