Texas Instruments SN74ALS259N Handleiding

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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

•8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With

Storage

•Asynchronous Parallel Clear

•Active-High Decoder

•Enable/Disable Input Simplifies Expansion

•Expandable for n-Bit Applications

•Four Distinct Functional Modes

•Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These 8-bit addressable latches are designed for

general-purpose storage applications in digital

systems. Specific uses include working registers,

serial-holding registers, and active-high decoders

or demultiplexers. They are multifunctional

devices capable of storing single-line data in eight

addressable latches and being a 1-of-8 decoder or

demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

as shown in the function table. In the

addressable-latch mode, data at the data-in

terminal is written into the addressed latch. The

addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the

memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To

eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the

address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the

level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address

and data inputs.

The SN54ALS259 is characterized for operation over the full military temperature range of −55°C to 125°C. The

SN74ALS259 is characterized for operation from 0°C to 70°C.

Function Tables

FUNCTION

INPUTS OUTPUT OF

ADDRESSED

EACH

OTHER

FUNCTION

CLR G

ADDRESSED

LATCH

OTHER

OUTPUT

FUNCTION

H L D QiO Addressable latch

H H QiO QiO Memory

L LL D 8-line demultiplexer

L H L L Clear

D = the level at the data input.

QiO = the level of Q

i (i = Q, 1, . . . 7 as appropriate) before the indicated

steady-state input conditions were established.

SN54ALS259 . . . J PACKAGE

SN74ALS259 . . . D OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

SN54ALS259 . . . FK PACKAGE

(TOP VIEW)

Q5 CLR

GND

NC − No internal connection

GND

VCC

CLR

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

SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Function Tables (Continued)

LATCH SELECTION

SELECT INPUTS

LATCH

S2 S1 S0

LATCH

ADDRESSED

L L L 0

L L H 1

L H L 2

L H H 3

H L L 4

H L H 5

H H L 6

H H H 7

logic symbol†

8M 0

Z10

9, 0D Q0

CLR

10, 0R

9, 1D Q1

10, 1R

9, 2D Q2

10, 2R

9, 3D Q3

10, 3R

9, 4D Q4

10, 4R

9, 5D Q5

10, 5R

9, 6D Q6

10, 6R

9, 7D Q7

10, 7R

†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

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

SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

logic diagram (positive logic)

CLR

Pin numbers shown are for the D, J, and N packages.

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74ALS259N
Breedte:	19.69 mm
Diepte:	6.6 mm
Hoogte:	4.57 mm
Breedte verpakking:	13.97 mm
Diepte verpakking:	506 mm
Hoogte verpakking:	11.23 mm
Soort:	Logic IC
Type verpakking:	PDIP
Aantal per verpakking:	25 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	0 - 70 °C
Aantal pinnen:	16
Breedte (met pennen):	19.69 mm
Diepte (met pennen):	10.92 mm
Hoogte (met pennen):	8.26 mm