Texas Instruments SN74221N Handleiding

Texas Instruments Niet gecategoriseerd SN74221N

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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DDual Versions of Highly Stable SN54121

and SN74121 One Shots

DSN54221 and SN74221 Demonstrate

Electrical and Switching Characteristics

That Are Virtually Identical to the SN54121

and SN74121 One Shots

DPinout Is Identical to the SN54123,

SN74123, SN54LS123, and SN74LS123

DOverriding Clear Terminates Output Pulse

TYPE

MAXIMUM

OUTPUT

PULSE

LENGTH(S)

SN54221 21

SN74221 28

SN54LS221 49

SN74LS221 70

description/ordering information

The ’221 and ’LS221 devices are dual

multivibrators with performance characteristics

virtually identical to those of the ’121 devices.

Each multivibrator features a negative-transition-

triggered input and a positive-transition-triggered

input, either of which can be used as an inhibit

input.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP N

T b

SN74221N SN74221N

PDIP − N Tube SN74LS221N SN74LS221N

0 C°C t 70°

SOIC D

Tube SN74LS221D

LS221

0 C°C to 70°SOIC − D Tape and reel SN74LS221DR LS221

SOP − NS Tape and reel SN74LS221NSR 74LS221

SSOP − DB Tape and reel SN74LS221DBR LS221

CDIP J

Tube

SNJ54221J SNJ54221J

−55° °C to 125 C CDIP − J Tube SNJ54LS221J SNJ54LS221J

55 CC to 125

LCCC − FK Tube SNJ54LS221FK SNJ54LS221FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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#'$#1  "** (""!'#'$,

3 2 1 20 19

9 10 11 12 13

1Cext

2CLR

1CLR

2Cext

ext

GND

1CLR

2Cext

2Rext

/Cext

GND

VCC

1Rext/Cext

1Cext

2CLR

SN54221, SN54LS221 . . . J PACKAGE

SN74221 . . . N PACKAGE

SN74LS221 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

SN54LS221 . . . FK PACKAGE

(TOP VIEW)

ext/Cext

2R /Cext

NC − No internal connection

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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  

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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input

pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with

transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high

immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing

components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration

relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing

appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved

that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent

of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics

waveforms.

Pulse-width stability is achieved through internal compensation and is virtually independent of V CC and

temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing

capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,

2 kΩ to 40 k to 70 kΩ for the SN74221, 2 kΩ Ω for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).

Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In

circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ

can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air

temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher

duty cycles are available if a certain amount of pulse-width jitter is allowed.

The variance in output pulse width from device to device typically is less than ±0.5% for given external timing

components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width

versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123

so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by

merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.

FUNCTION TABLE

(each monostable multivibrator)

INPUTS OUTPUTS

CLR A B Q Q

L X X L H

X HH X L

X HX L L

H L ↑††

H H↓††

↑‡L H † †

†Pulsed-output patterns are tested during

AC switching at 25°C with R

ext = 2 kΩ, and

Cext = 80 pF.

‡This condition is true only if the output of

the latch formed by the two NAND gates

has been conditioned to the logic 1 state

prior to CLR going high. This latch is

conditioned by taking either A high or

B low while CLR is inactive (high).

   

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    

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing component connections

VCC

Rext

To Cext

Terminal

To Rext/Cext

Terminal

NOTE: Due to the internal circuit, the R

ext/Cext terminal never is more positive than the C

ext terminal.

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74221N
Breedte:	19.69 mm
Diepte:	6.6 mm
Hoogte:	4.57 mm
Breedte verpakking:	13.97 mm
Diepte verpakking:	506 mm
Hoogte verpakking:	11.23 mm
Soort:	Logic IC
Type verpakking:	PDIP
Aantal per verpakking:	25 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	0 - 70 °C
Aantal pinnen:	16
Breedte (met pennen):	19.69 mm
Diepte (met pennen):	10.92 mm
Hoogte (met pennen):	8.26 mm