Texas Instruments 74ACT11032N Handleiding

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74ACT11032

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCAS008C – JULY 1987 – REVISED APRIL 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Center-Pin VCC and GND Congurations to

Minimize High-Speed Switching Noise

EPIC

(Enhanced-Performance Implanted

CMOS) 1-m Process

500-mA Typical Latch-Up Immunity at 125°C

Package Options Include Plastic

Small-Outline Packages (D), Plastic Shrink

Small-Outline Packages (DB), Plastic Thin

Shrink Small-Outline Packages (PW), and

Standard Plastic 300-mil DIPs (N)

description

This device contains four independent 2-input OR gates. It performs the Boolean function Y = A + B or

YA B• in positive logic.

The 74ACT11032 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS OUTPUT

A BY

H XH

X HH

L LL

logic symbol†

†This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

7

6

3

2

4B

4A

3B

3A

2B

2A

1B

1A

4Y

3Y

2Y

1Y

8

9

10

11

14

15

16

1≥

logic diagram (positive logic)

1Y

1A

1B

2Y

2A

2B

3Y

3A

3B

4Y

4A

4B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1A

1Y

2Y

GND

GND

3Y

4Y

4B

1B

2A

2B

VCC

VCC

3A

3B

4A

D, DB, N, OR PW PACKAGE

(TOP VIEW)

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Product specificaties