Texas Instruments CDCR83A Handleiding

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FEATURES

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24

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V

DD

IR

REFCLK

V

DD

P

GNDP

GNDI

PCLKM

SYNCLKN

GNDC

V

DD

C

V

DD

IPD

STOPB

PWRDNB

S0

S1

V

DD

O

GNDO

CLK

NC

CLKB

GNDO

V

DD

O

MULT0

MULT1

S2

DBQ PACKAGE

(TOP VIEW)

NC − No internal connection

DESCRIPTION

CDCR83A

SCAS811–AUGUST2005

DIRECTRAMBUS™CLOCKGENERATOR

•400-MHzDifferentialClockSourceforDirect

Rambus™MemorySystemsforan800-MHz

DataTransferRate

•Fail-SafePowerUpInitialization

•SynchronizestheClockDomainsofthe

RambusChannelWithanExternalSystemor

ProcessorClock

•ThreePowerOperatingModestoMinimize

PowerforMobileandOtherPower-Sensitive

Applications

•OperatesFromaSingle3.3-VSupplyand

120mWat300MHz(Typ)

•PackagedinaShrinkSmall-OutlinePackage

(DBQ)

•SupportsFrequencyMultipliers:4,6,8,16/3

•NoExternalComponentsRequiredforPLL

•SupportsIndependentChannelClocking

•SpreadSpectrumClockingTracking

CapabilitytoReduceEMI

•DesignedforUseWithTI's133-MHzClock

SynthesizersCDC924andCDC921

•Cycle-CycleJitterIsLessThan50psat

400MHz

•CertifiedbyGigatestLabstoExceedthe

RambusDRCGValidationRequirement

•SupportsIndustrialTemperatureRangeof

–40°Cto85°C

TheDirectRambusclockgenerator(DRCG)providesthenecessaryclocksignalstosupportaDirectRambus

memorysubsystem.ItincludessignalstosynchronizetheDirectRambuschannelclocktoanexternalsystemor

processorclock.ItisdesignedtosupportDirectRambusmemoryonadesktop,workstation,server,andmobile

PCmotherboards.DRCGalsoprovidesanoff-the-shelfsolutionforabroadrangeofDirectRambusmemory

applications.

TheDRCGprovidesclockmultiplicationandphasealignmentforaDirectRambusmemorysubsystemtoenable

synchronouscommunicationbetweentheRambuschannelandASICclockdomains.InaDirectRambus

memorysubsystem,asystemclocksourceprovidestheREFCLKandPCLKclockreferencestotheDRCGand

memorycontroller,respectively.TheDRCGmultipliesREFCLKanddrivesahigh-speedBUSCLKtoRDRAMs

andthememorycontroller.GearratiologicinthememorycontrollerdividesthePCLKandBUSCLKfrequencies

byratiosMandNsuchthatPCLKM=SYNCLKN,whereSYNCLK=BUSCLK/4.TheDRCGdetectsthephase

differencebetweenPCLKMandSYNCLKNandadjuststhephaseofBUSCLKsuchthattheskewbetween

PCLKMandSYNCLKNisminimized.ThisallowsdatatobetransferredacrosstheSYNCLK/PCLKboundary

withoutincurringadditionallatency.

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas

Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

DIRECTRAMBUS,RambusaretrademarksofRambusInc.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.

Copyright©2005,TexasInstrumentsIncorporated

ProductsconformtospecificationsperthetermsoftheTexas

Instrumentsstandardwarranty.Productionprocessingdoesnot

necessarilyincludetestingofallparameters.

Product specificaties