Microchip SY89474U Handleiding

Microchip Niet gecategoriseerd SY89474U

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SY89474U
Precision LVDS 2:1 Multiplexer with 1:2
Fanout and Internal Termination
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2005 M9999-081105
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89474U is a 2.5V precision, high-speed 2:1
differential MUX capable of processing clocks up to
2.5GHz and data up to 2.5Gbps.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that directly interfaces to any
differential signal (AC- or DC-coupled) as small as
100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
output is 325mV LVDS with fast rise/fall times guaranteed
to be less than 150ps.
The SY89474U operates from a 2.5V Âą5% supply and is
guaranteed over the full industrial temperature range of
-40°C to +85°C. The SY89474U is part of Micrel’s high-
speed, Precision EdgeÂŽ product line. For multiple clock
switchover solutions, please refer to the SY89840U–
SY89845U fa mily.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
Functional Block Diagram
Precision EdgeÂŽ
Features
•Selects between two input channels and provides two
copies of the selected input
•Guaranteed AC performance over temperature and
supply voltage:
−DC to 2.5Gbps data throughput
−DC to 2.5GHz fMAX (clock)
−<470ps In-to-Out tpd
−<150ps tr/tf
−<20ps output-to-output skew
•Unique, patent-pending input isolation design
minimizes crosstalk
•Ultra-low jitter design:
−<1psRMS random jitter
−<10psPP deterministic jitter
−<1psRMS cycle-to-cycle jitter
−<10psPP total jitter (clock)
−<0.7psRMS crosstalk induced jitter
•Unique patent-pending input termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
•325mV LVDS output swing
•2.5V ±5% supply voltage
•−40°C to +85°C industrial temperature range
•Available in 24-pin (4mm x 4mm) QFN package
Applications
•Clock switchover
•Data distribution
Markets
•LAN/WAN
•Enterprise Servers
•ATE
•Test and Measurement
Precision Edge is a registered trademark of Micrel, Inc.
Micrel, Inc. SY89474U
August 2005 2 M9999-081105
hbwhelp@micrel.com or (408) 955-1690
Ordering Information (1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY89474UMG QFN-24 Industrial 474U with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY89474UMGTR (2) QFN-24 Industrial 474U with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
24-Pin QFN
Micrel, Inc. SY89474U
August 2005 3 M9999-081105
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number Pin Name Pin Function
5, 2,
23, 20
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. They accept AC- or DC-coupled signals as small as 100mV (200mVpp).
Note that these inputs will default to an undetermined state if left open. Each pin
of a pair internally terminates to a VT pin through 50Ω. Please refer to the “Input
Interface Applications” section for more details.
3, 21 VREF-AC0,
VREF-AC1
Reference Voltage: These outputs bias to V
CC -1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01ÂľF low ESR capacitor to VCC. Maximum sink/source
current is Âą1.5mA. Due to the limited drive capability, the VREF-AC pin is only
intended to drive its respective VT pin. Please refer to the “Input Interface
Applications” section for more details.
4, 22 VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
1, 6, 9, 10, 13,
19, 24 VCC Positive Power Supply: Connect to +2.5V Âą5% power supply. Bypass with
0.1ÂľF//0.01ÂľF low ESR capacitors as close to VCC pins as possible.
7, 8
11, 12
Q0, /Q0
Q1, /Q1
Differential Outputs: These differential LVDS output pairs are a logic function of
the IN0, IN1, and SEL inputs. Please refer to the truth table below for details.
Unused output pairs should be terminated with 100Ω across the outputs.
15 SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor
and will default to a logic HIGH state if left open. V
TH = VCC/2. Please refer to the
“Timing Diagram” section for more details.
14, 17, 18 GND,
Exposed Pad
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
Truth Table
INPUTS OUTPUTS
IN0 /IN0 IN1 /IN1 SEL Q /Q
0 1 X X 0 0 1
1 0 X X 0 1 0
X X 0 1 1 0 1
X X 1 0 1 1 0

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: SY89474U

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