Microchip SY58020U Handleiding

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SY58020U

6GHz, 1:4 CML Fanout Buffer/Translator

with Internal I/O Termination

P. recision Edge isrademarkf Micrel, Inc a t o

Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 9440800 • fax + 1 (408) 4741000 • San --http://www.micrel.com

October 27

, 2014 Revision 5.0

tcghe[email protected]-or (408) 9551690

General Description

The SY58020U is a 2.5V/3.3V precision, high-speed, fully

differential 1:4 CML fanoutbuffer. Optimized to provide

four identical output copies with less than 15ps of skew

and 27fsRMS of typical additive phase jitter, the SY58020U

can process clock signals as fast as 6GHz.

The differential input includes Micrel’s unique, 3-pin input

termination architecture interfaces to differential that

LVPECL, LVDS, and CML signals (ACor DCcoupled) as - -

small as 100mV without any levelshifting or termination -

resistor networks in the signal path. For ACcoupled input -

interface applications, an onoutput reference -board

voltage (VREF-AC) is provided to bias the VT pin. The outputs

are optimized to drive 400mV typical swing into 50Ω loads,

with extremely fast rise/fall times guaranteedto be less

than 60ps.

The SY58020U operates from a 2.5V ±5% supply or 3.3V

±10% supply and is guaranteed over the full industrial

temperature range (40°C to +85°C). For applications that –

require LVPECL outputs, consider the SY58021U or

SY58022U 1:4 fanout buffer with 800mV and 400mV

output swing, respectively. The SY58020U is part of

Micrel’s high-speed, Precision Edge®product line.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Features

•Precision 1:4, 400mV CML fanout buffer

•Guaranteed AC performance over temperature/voltage:

−> 6GHz fMAXclock

−< 60ps tr/ tftimes

−< 250ps tpd

−< 15ps max. skew

•Low-jitter performance:

−27fsRMS typical additive phase jitter

•Accepts an input signal as low as 100mV

•Unique patented input termination and VT pin accepts

DC--coupled and ACcoupled differential inputs:

LVPECL, LVDS, and CML

•50Ω source terminated CML outputs

•Power supply 2.5V ±5% and 3.3V ±10%

•Industrial temperature range: –40°C to +85°C

•Available in 16-pin (3mm x 3mm) QFN package

Applications

•All SONET and All GigE clock distribution

•Fibre Channel clock and data distribution

•Backplane distribution

•Data distribution: OC--48, OC48+FEC, XAUI

•High-end, low skew, multiprocessor synchronous clock

distribution

Functional Block Diagram Typical Performance

Product specificaties