Microchip SY54020R Handleiding

Microchip Niet gecategoriseerd SY54020R

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SY54020R
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout
Buffer with /EN and Fail-Safe Input
3.2Gbps, 2.5GHz
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2009 M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY54020R is a fully differential, low voltage
1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low
Enable (/EN) and Fail-Safe Input (FSI). The Enable is
synchronous so that the outputs will only be
enabled/disabled when they are already in the LOW
state. This avoids any chance of generating a runt clock
pulse when the device is enabled/disabled as can
happen with an asynchronous control. When this device
is used as a clock fanout, disabling the downstream
clock may reduce system power. FSI is a special circuit
designed to sense the amplitude of the input signal and
to latch the output when an invalid or no signal is
present at the input. The SY54020R can process clock
signals up to 2.5 GHz or data patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals as small as 100mV
(200mVpp) without any level-shifting or termination
resistor networks in the signal path. For AC-coupled
input interface applications, an internal voltage
reference is provided to bias the VT pin. The outputs are
CML, with extremely fast rise/fall times guaranteed to be
less than 100ps.
The SY54020R operates from a 2.5V ±5% core supply
and a 1.2V, 1.8V or 2.5V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C).
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
• 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with FSI
• Active-low Enable (/EN) input to disable the outputs
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps Data throughput
– DC-to > 2.5GHz Clock throughput
– <400 ps propagation delay (IN-to-Q)
– <20ps within-device skew
– <100 ps rise/fall times
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
• High-speed CML outputs
• 2.5V ±5% VCC , 1.2/1.8V/2.5V ±5% VCCO power supply
operation
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Applications
• SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Micrel, Inc. SY54020R
April 2009 2 M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
Ordering Information (1)
Part Number Package
Type
Operating
Range
Package Marking Lead
Finish
SY54020RMG MLF-16 Industrial 020R with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY54020RMGTR(2) MLF-16 Industrial 020R with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin MLF® (MLF-16)
Micrel, Inc. SY54020R
April 2009 3 M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number Pin Name Pin Function
2,3
IN, /IN
Differential Input: This input pair is the differential signal input to the device. It
accepts differential signals as small as 100mV
(200mVPP). Each input pin internally
terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold
(typical 30mV), the Fail-Safe Input (FSI) feature will guarantee a stable output by
latching the output to its last valid state. Please refer to the “Interface Applications”
section for more details.
1
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC coupling, bypass VT with 0.1µF low ESR capacitor to
VCC. See “Interface Applications” subsection and Figure 2a.
4 /EN Single-ended TTL/CMOS-compatible input functions as a synchronous output
enable. The synchronous enable ensures that enable/disable will only occur when
the outputs are in a logic LOW state. The input -switching threshold is Vcc/2. Note
that this input is internally connected to a 25kΩ pull-down resistor and will default to
a logic LOW state (Enabled) if left open. Outputs are disabled when /EN is high.
See Figure 1b for more details.
16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to
the VCC pin as possible. Supplies input and core circuitry.
8,13 VCCO Output Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the V
CCO
pin as possible. Supplies the output buffers.
5 GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
15,14
12,11
10,9
7,6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
CML Differential Output Pairs: Differential buffered copy of the input signal. The
output swing is typically 380mV. See “Interface Applications” subsection for
termination information.
Truth Table
IN /IN /EN Q /Q
0 1 0 0 1
1 0 0 1 0
X X 1 0(1) 1(1)
Note:
1. See timing diagram, Figure 1b.

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: SY54020R

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