Texas Instruments CD74HCT670E Handleiding

Texas Instruments Niet gecategoriseerd CD74HCT670E

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Data sheet acquired from Harris Semiconductor

SCHS195C

Features

• Simultaneous and Independent Read and Write

Operations

• Expandable to 512 Words of n-Bits

• Three-State Outputs

• Organized as 4 Words x 4 Bits Wide

• Buered Inputs

• Typical Read Time = 16ns for ’HC670 V

CC = 5V, CL =

15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤µ1 A at V

OL, VOH

Description

The ’HC670 and CD74HCT670 are 16-bit register files

organized as 4 words x 4 bits each. Read and write address

and enable inputs allow simultaneous writing into one location

while reading another. Four data inputs are provided to store

the 4-bit word. The write address inputs (WA0 and WA1)

determine the location of the stored word in the register.

When write enable (WE) is low the word is entered into the

address location and it remains transparent to the data. The

outputs will reflect the true form of the input data. When (WE)

is high data and address inputs are inhibited. Data acquisition

from the four registers is made possible by the read address

inputs (RA1 and RA0). The addressed word appears at the

output when the read enable (RE) is low. The output is in the

high impedance state when the (RE) is high. Outputs can be

tied together to increase the word capacity to 512 x 4 bits.

Pinout

CD54HC670

(CERDIP)

CD74HC670, CD74HCT670

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(oC) PACKAGE

CD54HC670F3A -55 to 125 16 Ld CERDIP

CD74HC670E -55 to 125 16 Ld PDIP

CD74HC670M -55 to 125 16 Ld SOIC

CD74HC670MT -55 to 125 16 Ld SOIC

CD74HC670M96 -55 to 125 16 Ld SOIC

CD74HCT670E -55 to 125 16 Ld PDIP

CD74HCT670M -55 to 125 16 Ld SOIC

CD74HCT670MT -55 to 125 16 Ld SOIC

CD74HCT670M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

RA1

RA0

GND

VCC

WA0

WA1

January 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC670, CD74HC670,

CD74HCT670

High-Speed CMOS Logic

4x4 Register File

[ /Title

(CD74H

C670,

CD74H

CT670)

/Subject

(High-

Speed

CMOS

Logic

4x4 Reg-

ister

Functional Diagram

10 Q0

5 14 13

RA1

RA0

WA0

WA1

WRITE MODE SELECT TABLE

OPERATING

MODE

INPUTS INTERNAL

LATCHES

(NOTE 1)WE DN

Write Data L L L

L H H

Data Latched H X No Change

NOTE:

1. The Write Address (WA0 and WA1) to the “internal latches” must

be stable while WE is LOW for conventional operation.

READ MODE SELECT TABLE

OPERATING

MODE

INPUTS

OUTPUT

INTERNAL

LATCHES

(NOTE 2)

Read L L L

L H H

Disabled H X (Z)

NOTE:

2. The selection of the “internal latches” by Read Address (RA0 and

RA1) are not constrained by RE operation.WE or

H = High Voltage Level

L = Low Voltage Level

X= Don’t Care

Z = High Impedance “O” State

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V 20mA. . . . . . . . . . . . . . . . . . . . . .±

DC Output Diode Current, IOK

For VO < -0.5V or V

O > VCC + 0.5V 20mA . . . . . . . . . . . . . . . . . . . . ±

DC Drain Current, per Output, I

For -0.5V < VO < V

CC + 0.5V 35mA. . . . . . . . . . . . . . . . . . . . . . . . . . ±

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or V

O < VCC + 0.5V 25mA . . . . . . . . . . . . . . . . . . . . ±

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, T

A . . . . . . . . . . . . . . . . . . . . . . -55

oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θ

JA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage

VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage

VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - - - - - - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - - - - - - - - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current

IIVCC or

GND

- 6 - - ± ± ± µ0.1 - 1 - 1 A

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	CD74HCT670E
Breedte:	19.69 mm
Diepte:	6.6 mm
Hoogte:	4.57 mm
Breedte verpakking:	13.97 mm
Diepte verpakking:	506 mm
Hoogte verpakking:	11.23 mm
Soort:	Logic IC
Type verpakking:	PDIP
Aantal per verpakking:	25 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	-55 - 125 °C
Aantal pinnen:	16
Breedte (met pennen):	19.69 mm
Diepte (met pennen):	10.92 mm
Hoogte (met pennen):	8.26 mm