Microchip MIC5373/83 Handleiding

Microchip Niet gecategoriseerd MIC5373/83

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MIC5373/83 Evaluation Board
Triple 200mA µCap
LDO in 2.5 x 2.5 Thin MLF®
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2010 M9999-092410-A
General Description
The MIC5373/83 is an advanced, general purpose, triple-
output linear regulator offering high Power Supply
Rejection (PSRR) in a tiny 16-pin, 2.5mm x 2.5mm Thin
MLF®
package. The MIC5373/83 is capable of 200mA
from each output and offers high PSRR, making it an ideal
solution for any portable electronic application. The
MIC5373 provides independent control active high enables
for each of the LDO outputs. The MIC5383 provides active
low enables.
The MIC5373/83 incorporates a Power-On-Reset (POR)
supervisor with adjustable delay time set by an external
capacitor, and an independent input pin to monitor any
voltage level. Once high, the POR output can be asserted
low again by enabling the Manual Reset (MR) pin. When
the MR pin is restored low, the POR output will re-time the
delay set by the external delay capacitor.
An input capacitor is required when the power supply is
more than four inches from the device. The evaluation
board includes an input capacitor of 10µF to compensate
for long inductive test leads.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Requirements
The MIC5373/83 evaluation board requires two power
supplies. The first supply must be able to provide a
minimum of 800mA with a voltage range of 1.7V − 5.5V to
the INLDO pins. The second supply for V BIAS must be able
to supply a few mA with a voltage range of 2.5V − 5.5V.
For input voltages of 2.5V or greater, a single supply can
be used for both the INLDO and VBIAS. The output load can
be either active or passive.
Precautions
The MIC5373/83 evaluation board does not have reverse
polarity protection. Applying a negative voltage to the
INLDO or VBIAS terminals may damage the device.
Getting Started
• Connect an External Supply to V BIAS. Apply the
desired input voltage to the VBIAS (J1) and ground (J2)
terminal of the evaluation board, paying careful attention
to polarity and supply voltage (2.5V ≤ VBIAS ≤ 5.5V).
• Connect an External Supply to INLDO. Apply the
desired input voltage to the INLDO (J4 for LDO1/2, J5
for LDO3) and ground (J2, J6, and J13) terminals of the
evaluation board, paying careful attention to polarity and
supply voltage (1.7V ≤ INLDO ≤ 5.5V). An ammeter can
be placed between the input supply and the INLDO
terminal of the evaluation board. Ensure that the supply
voltage is monitored at the INLDO terminals. The
ammeter and/or power-lead resistance can reduce the
voltage supplied to the input.
• Enable/Disable the MIC5373/83. The MIC5373
evaluation board is supplied with 100KΩ pull-up
resistors (R1, R2, R3) on the EN1, EN2, and EN3 pins
for default on state. While the MIC5383 has pull-down
resistors (R1b, R2b, R3b) for default on state. To
disable the MIC5373 jumper the enable terminal (J15 for
LDO1, J16 for LDO2, and J17 for LDO3) to GND. To
disable the MIC5383 jumper the enable terminal (J15 for
LDO1, J16 for LDO2, and J17 for LDO3) to V BIAS. The
enable pins must be either pulled high or low. Leaving
enable pins floating will cause the regulator to operate in
an indeterminate state.
• Connect the Load. Connect the loads to the V OUT
Terminals (J7 for LDO1, J8 for LDO2 and J9 for LDO3)
and Ground Terminals (J2, J6, J11, or J13). The loads
can be either passive (resistor) or active (electronic
load). Be sure to monitor the output voltage at the V OUT
(J7, J8 and J9) terminals.
Ordering Information
Part Number Description
MIC5373-MG4YMT EV
Triple-Output LDO Evaluation
Board. VOUT1 = 2.8V, VOUT2 = 1.8V,
VOUT3 = 1.2V. Active High Enables.
MIC5383-MG4YMT EV
Triple-Output LDO Evaluation
Board. VOUT1 = 2.8V, VOUT2 = 1.8V,
VOUT3 = 1.2V. Active Low Enables.
Micrel, Inc. MIC5373/83 Evaluation Board
September 2010 2 M9999-092410-A
Application Information Delay (DLY)
The Delay (DLY) pin is used to set the POR delay time.
Adding a capacitor to this pin (C10) adjusts the delay of
the POR signal. When the POR_IN flag is triggered, a
constant 1.25µA current begins to charge the external
capacitor tied to the DLY pin. When the capacitor reaches
1.25V the POR will be pulled high by the external pull up
resistor. The equation to calculate the charge time is
shown:
Power-On-Reset (POR)
The Power-On-Reset (POR) pin is an open drain output. A
100kΩ pull up resistor to VBIAS is provided. POR is
asserted high when the voltage at DLY reaches 1.25V. A
delay can be added by placing a capacitor from the DLY
pin to ground.
Power-On-Reset Input (POR_IN)
The Power-On-Reset Input (POR_IN) pin compares any
voltage to an internal 0.9V reference. This function can be
used to monitor any of the LDO outputs or any external
voltage rail. When the monitored voltage is greater than
0.9V, the POR_IN flag will internally trigger a 1.25µA
source current to charge the external capacitor at the DLY
pin. A resistor divider network (R5 – R8) is provided to
divide down the monitored voltage to be compared with
the 0.9V at the POR_IN. The monitored voltage can be
selected by changing the jumpers (TP2 for VOUT3, TP3 for
VOUT2, and TP4 for VOUT1). The resistor divider network can
be changed to set the trigger point to any voltage level. A
small decoupling capacitor (C9) of 10nF is recommended
between POR_IN and ground to reject high-frequency
noise that might interfere with the POR circuit. Do not
leave the POR_IN pin floating if the POR output is being
monitored. A floating POR_IN pin will cause an
indeterminate state on the POR pin.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=−6
DLY
DELAY 10 x 1.25
C1.25V x
(s)
t
The delay time (tDELAY) is in seconds, the delay voltage is
1.25V internally, and the external delay capacitance (C DLY)
is in microfarads. For a 1µF delay capacitor, tDELAY will be
1s. A capacitor at the DLY pin is recommended when the
POR function is used in order to prevent unexpected
triggering of the POR signal in noisy systems.
Manual Reset (MR)
The Manual Reset (MR) pin resets the output of POR and
DLY generator regardless if the monitored voltage is in
regulation or not. Applying a voltage greater than 1.2V on
the MR pin will cause the POR voltage to be pulled low.
When a voltage below 0.2V is applied to the MR pin, the
internal 1.25µA will begin to charge the DLY pin until it
reaches 1.25V. When the DLY pin reaches 1.25V, the
POR voltage will be pulled high by the pull up external
resistor again. Do not leave the MR pin floating. A 100kΩ
pull-down resistor (R4) is provided on the evaluation board
to ensure that the MR is disabled.
Micrel, Inc. MIC5373/83 Evaluation Board
September 2010 3 M9999-092410-A
MIC5373 Evaluation Board Schematic
Bill of Materials
Item Part Number Manufacturer Description Qty.
C1-C3 C1608X5R0J106K TDK(1) 10μF, Ceramic, 6.3V, X5R, Size 0603 Capacitor 3
GRM155R1A1055KE19D Murata(2) 1μF, Ceramic, 10V, X5R, Size 0402 Capacitor
0402ZD105KAT2A AVX(3) 1μF, Ceramic, 10V, X5R, Size 0402 Capacitor
C5 − C7
LMK105BJ105KV-F Taiyo Yuden(4) 1μF, Ceramic, 10V, X5R, Size 0402 Capacitor
3
R1 − R5, R10 CRCW0402100KFKEA Vishay(5) 100KΩ, 1%, 1/16W, Size 0402 Resistor 6
R6 CRCW0402180KFKEA Vishay(5) 180KΩ, 1%, 1/16W, Size 0402 Resistor 1
R7 CRCW040280K6FKEA Vishay(5) 80.6KΩ, 1%, 1/16W, Size 0402 Resistor 1
R8 CRCW040220K0FKEA Vishay(5) 20KΩ, 1%, 1/16W, Size 0402 Resistor 1
U1 MIC5373-MG4YMT Micrel, Inc.(6) High-Performance, Triple-Output, 200mA LDO 1
Notes:
1. TDK: www.tdk.com.
2. Murata: www.murata.com.
3. AVX: www.avx.com.
4. Taiyo Yuden: www.t-Yuden.com.
5. Vishay: www.vishay.com.
6. Micrel, Inc.: www.micrel.com

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: MIC5373/83

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