Texas Instruments SN74LV125APWR Handleiding

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SN74LV125A Quadruple Bus Buffer Gates With 3-State Outputs

1 Features

•2-V to 5.5-V VCC Operation

•Max tpd of 6 ns at 5 V

•Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

•Typical VOHV (Output VOH Undershoot)

> 2.3 V at VCC = 3.3 V, TA = 25°C

•Support Mixed-Mode Voltage Operation on

All Ports

• Ioff Supports Partial-Power-Down Mode Operation

•Latch-Up Performance Exceeds 250 mA Per

JESD 17

•ESD Protection Exceeds JESD 22

–4000-V Human-Body Model

–200-V Machine Model

–2000-V Charged-Device Model

2 Applications

•Flow Meters

•Solid State Drives (SSDs): Enterprise

•Power Over Ethernet (PoE)

•Programmable Logic Controllers

•Motor Drives and Controls

•Electronic Points of Sale

3 Description

The SN74LV125A quadruple bus buffer gate is

designed for 2-V to 5.5-V VCC operation.

Device Information

PART NUMBER(1) PACKAGEBODY SIZE (NOM)

SN74LV125A

DGV (TVSOP, 14)3.60 mm x 4.40 mm

D (SOIC, 14)8.65 mm × 3.90 mm

NS (SO, 14)10.20 mm x 5.30 mm

DB (SSOP, 14)6.20 mm x 5.30 mm

PW (TSSOP, 14)5.00 mm x 4.40 mm

(1)For all available packages, see the orderable addendum at

the end of the data sheet.

2A 2Y

2OE

1A 1Y

1OE

4A 4Y

4OE

3A 3Y

3OE

Simplified Schematic

SN74LV125A

SCES124O – DECEMBER 1997 – REVISED MAY 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product specificaties