Texas Instruments CD74HC533E Handleiding

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1

Data sheet acquired from Harris Semiconductor

SCHS187C

Features

•Common Latch-Enable Control

•Common Three-State Output Enable Control

•Buered Inputs

•Three-State Outputs

•Bus Line Driving Capacity

•Typical Propagation Delay = 13ns at V

CC = 5V,

CL = 15pF, TA = 25oC (Data to Output)

•Fanout (Over Temperature Range)

-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . .-55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL

Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il≤µ1A at VOL, VOH

Description

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are

high-speed Octal Transparent Latches manufactured with

silicon gateCMOS technology.They possessthe lowpower

consumption of standard CMOS integrated circuits, as well as

the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch

enable (LE) ishigh.When thelatchenable (LE)goes low the

datais latched. Theoutput enable (OE)controls the

three-state outputs. When the outputenable (OE) is high the

outputsarein the high impedance state.The latch operation

is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the

’HC563 and CD74HCT563 but have different pinouts. The

’HC533 and ’HCT533 are similarto the ’HC373 and ’HCT373;

the latter are non-inverting types.

Ordering Information

PART NUMBER

TEMP. RANGE

(oC) PACKAGE

CD54HC533F3A-55 to 12520 Ld CERDIP

CD54HC563F3A-55 to 12520 Ld CERDIP

CD54HCT533F3A-55 to 12520 Ld CERDIP

CD74HC533E-55 to 12520 Ld PDIP

CD74HC563E-55 to 12520 Ld PDIP

CD74HC563M-55 to 12520 Ld SOIC

CD74HCT533E-55 to 12520 Ld PDIP

CD74HCT563E-55 to 12520 Ld PDIP

CD74HCT563M-55 to 12520 Ld SOIC

January 1998 - Revised July 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright © 2003, Texas Instruments Incorporated

CD54/74HC533, CD54/74HCT533,

CD54/74HC563, CD74HCT563

High-Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

[ /Title

(CD74H

C533,

CD74H

CT533,

CD74H

C563,

CD74H

CT563)

/Subject

(High

Speed

Product specificaties