Texas Instruments ADS54J69 Handleiding

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Input Frequency (MHz)

Amplitude(dBFS)

050100150200250

-120

-100

-80

-60

-40

-20

0

D003

SNR = 73 dBFS

SFDR = 93 dBc

Non HD2, HD3 Spur = 94 dBc

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AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,

intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ADS54J69

SBAS713C–MAY2015–REVISEDJANUARY2017

ADS54J69Dual-Channel,16-Bit,500-MSPS,Analog-to-DigitalConverter

1

1Features

1

•16-BitResolution,Dual-Channel,500-MSPSADC

•IdleChannelNoiseFloor:–159dBFS/Hz

•SpectralPerformance(f

IN

=170MHzat–1dBFS):

–SNR:73dBFS

–NSD:–157dBFS/Hz

–SFDR:93dBc

–SFDR:94dBc(ExceptHD2,HD3,and

InterleavingTone)

•SpectralPerformance(f

IN

=310MHzat–1dBFS):

–SNR:71.7dBFS

–NSD:–155.7dBFS/Hz

–SFDR:81dBc

–SFDR:94dBc(ExceptHD2,HD3,and

InterleavingTone)

•ChannelIsolation:100dBcatf

IN

=170MHz

•InputFull-Scale:1.9V

PP

•InputBandwidth(3dB):1.2GHz

•On-ChipDither

•IntegratedDecimate-by-2Filter

•JESD204BInterfacewithSubclass1Support:

–1LaneperADCat10.0Gbps

–2LanesperADCat5.0Gbps

–SupportforMulti-ChipSynchronization

•PowerDissipation:1.35W/chat500MSPS

•72-PinVQFNPPackage(10mm×10mm)

2Applications

•RadarandAntennaArrays

•BroadbandWireless

•CableCMTS,DOCSIS3.1Receivers

•CommunicationsTestEquipment

•MicrowaveReceivers

•SoftwareDefinedRadio(SDR)

•Digitizers

•MedicalImagingandDiagnostics

3Description

TheADS54J69isalow-power,wide-bandwidth,16-

bit,500-MSPS,dual-channel,analog-to-digital

converter(ADC).Designedforhighsignal-to-noise

ratio(SNR),thedevicedeliversanoisefloorof

–159dBFS/Hzforapplicationsaimingforhighest

dynamicrangeoverawideinstantaneousbandwidth.

ThedevicesupportstheJESD204Bserialinterface

withdataratesupto10.0Gbps,supportingoneor

twolanesperADC.Thebufferedanaloginput

providesuniforminputimpedanceacrossawide

frequencyrangeandminimizessample-and-hold

glitchenergy.EachADCchannelisdirectly

connectedtoawidebanddigitaldown-converter

(DDC)block.TheADS54J69providesexcellent

spurious-freedynamicrange(SFDR)overalarge

inputfrequencyrangewithverylowpower

consumption.

TheJESD204Binterfacereducesthenumberof

interfacelines,allowinghighsystemintegration

density.Aninternalphase-lockedloop(PLL)

multipliestheADCsamplingclocktoderivethebit

clockthatisusedtoserializethe16-bitdatafrom

eachchannel.

DeviceInformation

PARTNUMBERPACKAGEBODYSIZE(NOM)

ADS54J69VQFNP(72)10.00mm×10.00mm

(1)Forallavailablepackages,seetheorderableaddendumat

theendofthedatasheet.

Spectrumat170-MHzIF

Product specificaties