Microchip SY89874U Handleiding

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 2018 Microchip Technology Inc.DS20006108B-page 1

SY89874U

Features

•Integrated Programmable Clock Divider and 1:2

Fanout Buffer

•Guaranteed AC Performance over Temperature

and Voltage:

->2.5GHz f

MAX

-<250ps t

r

/t

f

-<15ps Within-Device Skew

•Low Jitter Design:

-<10ps

PP

Total Jitter

-<1ps

RMS

Cycle-to-Cycle Jitter

•Unique Input Termination and V

T

Pin for

DC-Coupled and AC-Coupled Inputs; CML,

PECL, LVDS, and HSTL

•TTL/CMOS Inputs for Select and Reset

•100KEP-Compatible LVPECL Outputs

•Parallel Programming Capability

•Programmable Divider Ratios of 1, 2, 4, 8, and 16

•Low-Voltage Operation: 2.5V or 3.3V

•Output Disable Function

•–40°C to +85°C Temperature Range

•Available in 16-Pin (3mm x 3mm) QFN Package

Applications

•SONET/SDH Line Cards

•Transponders

•High-End Multiprocessor Sensors

General Description

This low-skew, low-jitter device is capable of accepting

a high-speed (e.g., 622MHz or higher) CML, LVPECL,

LVDS, or HSTL clock input signal and dividing down the

frequency using a programmable divider ratio to create

a frequency-locked, lower speed version of the input

clock. Available divider ratios are 2, 4, 8, and 16, or

straight pass-through. In a typical 622MHz clock

system this would provide availability of 311MHz,

155MHz, 77MHz, or 38MHz auxiliary clock

components.

The differential input buffer has a unique internal

termination design that allows access to the

termination network through a V

T

pin. This feature

allows the device to easily interface to different logic

standards. A V

REF-AC

reference is included for

AC-coupled applications.

The /RESET input asynchronously resets the divider. In

the pass-through function (divide by 1) the /RESET

synchronously enables or disables the outputs on the

next falling edge of IN (rising edge of /IN).

Package Type

SY89874U

3mm x 3mm QFN-16 (M)

(Top View)

13141516

12

11

10

9

1

2

3

4

8765

Q0

/Q0

Q1

/Q1

IN

VT

VREF-AC

/IN

S0

S1

VCC

GND

S2

NC

VCC

/RESET

2.5GHz, Any Differential In-to-LVPECL, Programmable Clock

Divider/Fanout Buffer with Internal Termination

Product specificaties