Microchip SY58052AU Handleiding

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SY58052AU

Ultra-Precision CML Data and Clock

Synchronizer with Internal Input and Output

Termination

PrecisionEdge

®

AnyGate and Precision Edge are registered trademarks of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • SanJose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

February 11,

2014

Revision 1.0

FOMhelp@micrel.comor (408) 955-1690

General Description

The SY58052AU is an ultra-fast, precision, low jitter data-

to-clock resynchronizer with a guaranteed maximum data

throughput of 10.7Gbps and a maximum clock of 10.7GHz.

TheSY58052AUis an idealsolution for backplane

retiming or retiming after the data passes through long

trace lengths. Serialdatacomes into thedatainput,and

theCMLoutput is synchronous to the input reference

clock’s rising edge.

The SY58052AUdifferentialinputsincludea unique,

internal termination design that allows access to the

terminationnetworkthrougha V

T

pin.This feature

allows the device to easily interface to different logic

standards, both AC- and DC-coupled, without external

resistor-bias and termination networks. The result is a

clean, stub-free, low-jitter interface solution. The

differential CML output is optimized for 50Ωenvironments

with internal 50Ωsource termination and a 400mV output

swing.

The SY58052AU operates from a 2.5V or 3.3V supply and

is guaranteed over the full industrial temperature range

(−40°C to +85°C). The SY58052AUis part of a Micrel’s

Precision Edge

®

product family.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com

.

Functional Block Diagram

Precision Edge

®

Features

•Resynchronize data to a reference clock

•Guaranteed AC performance over temperature and

voltage:

−DC-to >10.7Gbps data rate throughput

−DC-to >10.7GHz clock f

MAX

−160ps any in-to-out t

PD

−30ps typical Rise/Fall time

•Ultra low-jitter design:

−0.3ps

RMS

typical random jitter

−3ps

PP

typical deterministic jitter (data)

−<10ps

PP

total jitter (clock)

•Internal 50Ω input termination

•Unique input termination and V

T

pin accepts DC- and

AC-coupled inputs (CML, PECL)

•Internal 50Ω output source termination

•400mV CML output swing

•Power supply: 2.5V ±5% or 3.3V ±10%

•−40°C to +85°C industrial temperature range

•Available in a 3mm × 3mm 16-pin QFN package

Applications

•Data communications systems

•Serial OC-192, OC192+FEC data-to-clock realignment

•Parallel 10Gbps for OC-768

•All SONET OC-3 −OC-768 applications

•Fiber channel

•Gigabit Ethernet

•ATE

•Test and measurement

Product specificaties