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Section 13. Parallel Master Port (PMP)

HIGHLIGHTS

This section of the manual contains the following major topics:

13.1 Introduction .................................................................................................................. 13-2

13.2 Control Registers ......................................................................................................... 13-3

13.3 Master Modes of Operation ....................................................................................... 13-18

13.4 Slave Modes of Operation ......................................................................................... 13-41

13.5 Interrupts.................................................................................................................... 13-48

13.6 Operation in Power-Saving and Debug Modes.......................................................... 13-50

13.7 Effects of Various Resets........................................................................................... 13-50

13.8 Parallel Master Port Applications............................................................................... 13-51

13.9 Parallel Slave Port Application...................................................................................13-56

13.10 Direct Memory Access Support ................................................................................. 13-56

13.11 I/O Pin Control ........................................................................................................... 13-57

13.12 Related Application Notes..........................................................................................13-60

13.13 Revision History......................................................................................................... 13-61

PIC32 Family Reference Manual

13.1 INTRODUCTION

The Parallel Master Port (PMP) is a parallel 8-bit/16-bit I/O module specifically designed to

communicate with a wide variety of parallel devices such as communications peripherals, LCDs,

external memory devices and microcontrollers. Because the interfaces to parallel peripherals

vary significantly, the PMP module is highly configurable. The key features of the PMP module

include:

• Up to 24 programmable address lines

• Up to two Chip Select lines with two alternate Chip Selects for extended addressing

• Programmable strobe options:

- Individual read and write strobes or Read/write strobe with enable strobe

• Address auto-increment/auto-decrement

• Programmable address/data multiplexing

• Programmable polarity on control signals

• Legacy parallel slave port support

• Enhanced parallel slave support:

- Address support

- 4 bytes deep, auto-incrementing buffer

• Schmitt Trigger or TTL input buffers

• Programmable Wait states

• Freeze option for in-circuit debugging

• Separate configurable read/write registers or dual buffers for Master mode (not available on

all devices)

Figure 13-1: PMP Module Pinout and Connections to External Devices

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Parallel Master Port (PMP)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

PMA0

PMA14

PMA15

PMRD

PMWR

PMENB

PMRD/PMWR

PMCS1

PMA1

PMA<13:2>

(2)

PMALL

PMALH

PMCS2

EEPROM

Address Bus

Data Bus

Control Lines

LCD FIFO

Microcontroller

8-bit/16-bit data (with or without multiplexed addressing)

Up to 24-bit address

buffer

PMD<15:8>

(1)

PMA<7:0>

PMA<15:8>

PMD<7:0>

Parallel Master Port

PIC32

Note 1: The PMD<15:8> data pins are only available on PIC32 devices with 100 or more pins.

2: 24-bit addressing is available in Extended mode.

Section 13. Parallel Master Port (PMP)

13.2 CONTROL REGISTERS

The PMP module uses these Special Function Registers (SFRs):

•PMCON: Parallel Port Control Register

This register contains the bits that control much of the module’s basic functionality. A key bit

is the ON control bit, which is used to Reset, enable or disable the module.

When the module is disabled, all of the associated I/O pins revert to their designated I/O

function. In addition, any read or write operations active or pending are stopped, and the

BUSY bit is cleared. The data within the module registers is retained, including the data in

PMSTAT register. Therefore, the module could be disabled after a reception, and the last

received data and status would still be available for processing.

When the module is enabled, all buffer control logic is reset, along with PMSTAT.

All other bits in PMCON control address multiplexing enable various port control signals, and

select control signal polarity. These are discussed in detail in

13.3.1 “Parallel Master Port

Configuration Options”.

•PMMODE: Parallel Port Mode Register

This register contains bits that control the operational modes of the module. Master/Slave

mode selection and configuration options for both modes, are set by this register. It also

contains the universal status flag, BUSY, which is used in master modes to indicate that an

operation by the module is in progress.

Details on the use of the PMMODE bits to configure PMP operation are provided in

13.3 “Master Modes of Operation” and 13.4 “Slave Modes of Operation”.

•PMADDR: Parallel Port Address Register

This register contains the address to which outgoing data is to be written, as well as the Chip

Select control bits for addressing parallel slave devices. The PMADDR register is only used

in Single Buffer Master modes.

•PMDOUT: Parallel Port Data Output Register

This register is used only in Slave mode for buffered output data.

•PMDIN: Parallel Port Data Input Register

This register is used by the PMP module in both Master and Slave modes.

In Slave mode, this register is used to hold data that is asynchronously clocked in. Its

operation is described in 13.4.2 “Buffered Parallel Slave Port Mode”.

In Single Buffer Master modes, PMDIN is the holding register for both incoming and outgoing

data. Its operation in Master mode is described in 13.3.3 “Read Operation” and

13.3.4 “Write Operation”.

In Dual Buffer Master modes, the PMDIN is the holding register for the outgoing data. A

separate PMRDIN register holds the incoming data.

•PMAEN: Parallel Port Pin Enable Register

This register controls the operation of address and Chip Select pins associated with the PMP

module. Setting these bits allocates the corresponding microcontroller pins to the PMP

module; clearing the bits allocates the pins to port I/O or other peripheral modules

associated with the pin.

•PMSTAT: Parallel Port Status Register (Slave modes only)

This register contains status bits associated with buffered operating modes when the port is

functioning as a slave port. This includes overflow, underflow and full flag bit.

These flags are discussed in detail in 13.4.2 “Buffered Parallel Slave Port Mode”.

•PMWADDR: Parallel Port Write Address Register

This register contains the address to which outgoing data is to be written, as well as the Chip

Select control bits for addressing parallel slave devices. The PMWADDR register is only

used in Dual Buffer Master modes.

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	PIC32MX150F128D

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