Microchip PIC16F874A Handleiding

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1997 Microchip Technology Inc. DS31029A page 29-1
M
Instruction
Set
29
Section 29. Instruction Set
HIGHLIGHTS
This section of the manual contains the following major topics:
29.1 Introduction ..................................................................................................................29-2
29.2 Instruction Formats ......................................................................................................29-4
29.3 Special Function Registers as Source/Destination ......................................................29-6
29.4 Q Cycle Activity............................................................................................................29-7
29.5 Instruction Descriptions................................................................................................29-8
29.6 Design Tips ................................................................................................................29-45
29.7 Related Application Notes..........................................................................................29-47
29.8 Revision History .........................................................................................................29-48
PICmicro MID-RANGE MCU FAMILY
DS31029A-page 29-2 1997 Microchip Technology Inc.
29.1 Introduction
Each midrange instruction is a 14-bit word divided into an OPCODE which specifies the instruc-
tion type and one or more operands which further specify the operation of the instruction. The
midrange Instruction Set Summary in Table 29-1 lists the instructions recognized by the MPASM
assembler. The instruction set is highly orthogonal and is grouped into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and control operations
Table 29-2 gives the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a des-
tination designator. The file register designator specifies which file register is to be used by the
instruction.
The destination designator specifies where the result of the operation is to be placed. If 'd' is zero,
the result is placed in the W register. If 'd' is one, the result is placed in the file register specified
in the instruction.
For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the
bit aected by the operation, while 'f' represents the number of the file in which the bit is located.
For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.
All instructions are executed in one single instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an instruction. In these cases, the execution takes two
instruction cycles with the second cycle executed as an NOP. One instruction cycle consists of
four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execu-
tion time is 1 µs. If a conditional test is true or the program counter is changed as a result of an
instruction, the instruction execution time is 2
µs.
1997 Microchip Technology Inc. DS31029A-page 29-3
Section 29. Instruction Set
Instruction
Set
29
Table 29-1: Midrange Instruction Set
Mnemonic,
Operands Description Cycles
14-Bit Instruction Word Status
Aected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g.,
MOVF PORTB, 1
), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The sec-
ond cycle is executed as a NOP.

Product specificaties

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Categorie: Niet gecategoriseerd
Model: PIC16F874A

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