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User Guide

© 2023 Microchip Technology Inc. and its subsidiaries

DS50003555B - 1

Introducon (Ask a Queson)

This user guide describes the high-speed memory interfaces in SmartFusion

®

2 System-on-Chip (SoC) Field

Programmable Gate Array (FPGA) and IGLOO

®

2 FPGA devices. The high-speed interfaces Microcontroller/

Memory Subsystem Double-Data Rate (MDDR) subsystem and fabric DDR (FDDR) subsystem provide access

to DDR memories for high-speed data transfers. The DDR subsystem’s functionality, congurations, and their

use models are discussed in this user guide.

This user guide contains the following chapters:

1. MDDR Subsystem

2. Fabric DDR Subsystem

3. DDR Bridge

4. Soft Memory Controller Fabric Interface Controller

AddionalDocumentaon (Ask a Queson)

The following table describes additional documentation available for the SmartFusion 2 and IGLOO 2 devices.

For more information, see the SmartFusion 2 Documentation Page and IGLOO 2 Documentation Page online.

Table 1. Addional Documents

DocumentDescription

SmartFusion 2 System-on-Chip FPGAs Product Brief and IGLOO 2

FPGA Product Brief

This product brief provides an overview of SmartFusion

®

2 and IGLOO

®

2

family, features, and development tools.

IGLOO 2 and SmartFusion 2 DatasheetThis datasheet contains SmartFusion 2 and IGLOO 2 DC and switching

characteristics.

IGLOO 2 Pin Descriptions DatasheetThis document contains IGLOO 2 pin descriptions, package outline

drawings, and links to pin tables in Excel format.

SmartFusion 2 Pin Descriptions DatasheetThis document contains SmartFusion 2 pin descriptions, package outline

drawings, and links to pin tables in Excel format.

IGLOO 2 FPGA and SmartFusion 2 SoC FPGA Fabric User GuideSmartFusion 2 and IGLOO 2 FPGAs integrate fourth generation ash-based

FPGA fabric. The FPGA fabric is comprised of Logic Elements which consist

of a 4 input Look Up Table (LUT), includes embedded memories and

Mathblocks for DSP processing capabilities. This document describes the

SmartFusion 2 and IGLOO 2SmartFusion 2 and IGLOO 2 FPGA fabric

architecture, embedded memories, Mathblocks, fabric routing, and I/Os.

SmartFusion 2 Microcontroller SubsystemSmartFusion 2 devices integrate a hard microcontroller subsystem (MSS).

The MSS consists of a Arm

®

Cortex

®

-M3 processor with Embedded Trace

Macrocell (ETM), instruction cache, embedded memories, DMA engines,

communication peripherals, timers, Real-Time Counter (RTC), general

purpose I/Os, and FPGA fabric interfaces. This document describes the

SmartFusion 2 MSS and its internal peripherals.

IGLOO 2 High Performance Memory Subsystem User GuideIGLOO 2 devices integrate a hard High Performance Memory Subsystem

(HPMS) consists of embedded memories, DMA engines, and FPGA fabric

interfaces. This document describes the IGLOO 2 HPMS and its internal

peripherals.

SmartFusion 2 and IGLOO 2 FPGA High-Speed DDR

Interfaces User Guide

Product specificaties