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 2016 Microchip Technology Inc.DS00002054A-page 1

INTRODUCTION

This application note is intended to assist customers in designing a PCB using Microchip’s family of 10/100/1000 Mbps

Ethernet devices. This document provides recommendations regarding PCB layout, a critical component in maintaining

signal integrity and reducing EMI issues. The following topics are covered:

•General PCB Layout Guidelines on page 1

•USB Layout Guidelines on page 5

•Ethernet Layout Guidelines on page 5

•EMI Considerations on page 8

•ESD Considerations on page 9

•Troubleshooting Common Layout Issues on page 10

GENERAL PCB LAYOUT GUIDELINES

Power Supply Consideration

•Ensure adequate power supply ratings. Verify that all power supplies and voltage regulators can supply the

amount of current required.

•Power supply output ripple should be limited to less than 50 mV (less than 10mV for the best performance).

•Noise levels on all power and ground planes should be limited to less than 50mV.

•Ferrite beads should be rated for 4-6 times the amount of current they are expected to supply. Any derating over

temperature should also be accounted for.

Device Decoupling

•Every high-speed semiconductor device on the PCB assembly requires decoupling capacitors. One decoupling

capacitor for every power pin is necessary.

•The decoupling capacitor value is application dependent. Typical decoupling capacitor values may range from

0.001uF to 0.1uF.

•The total decoupling capacitance should be greater than the load capacitance presented to the digital output buf-

fers to prevent noise from being introduced into the supply.

•Typically, Class II dielectric capacitors are chosen for decoupling purposes. The first choice would be an X7R

dielectric ceramic capacitor for it's excellent stability and good package size versus capacitance characteristics.

The designer's second choice may be the X5R dielectric for its excellent stability. However, the X5R may be some-

what limiting in the package size versus capacitance characteristics. Low inductance is of the utmost importance

when considering decoupling capacitor characteristics.

•Each decoupling capacitor should be located as close as possible to the power pin that it is decoupling.

•All decoupling capacitor leads should be as short as possible. The best practice is directly connecting the capaci-

tors to the ground and power pin on top layer. If using vias becomes inevitable, pad-to-via connections should be

less than 10 mils in length. Trace connections should be as wide as possible to lower inductance.

•Strongly consider connecting the ground of all bypass capacitors with two vias to greatly reduce the inductance of

that connection.

AN2054

Gigabit Ethernet Design Guide

Author:Kiet Tran



Microchip Technology Inc.

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