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ASIC Test Oriented Simulation Manual
Introduction
A challenge of testing application-specific ICs is creating test patterns by IC-design engineers who do not have deep
knowledge of the test-equipment and the related requirements and restrictions.
This manual bridges the gap by providing explanations, examples, and the necessary information to successfully set
up and perform simulations, which must be usable for testprogram-generation. It also explains the Microchip-internal
transformation-flow and the tools involved.
Terminology
The following terms are used frequently to identify specific test features and constraints:
Terminology Description
ATE Automatic Test Equipment (ATE). A tester is an ATE.
DUT Device Under Test (DUT)
A hardware product verified on the tester. It can either be a die on a wafer or a
packaged part.
Wafer Probe Testing operation for die on wafers.
It uses an additional ATE named Prober and a DUT interface named Probe Card.
Final Test Testing operation for packaged parts after assembly.
It uses a DUT interface named Load Board.
Test Cycle The interval of time (also called period) in which a test vector is presented to the DUT.
The beginning of a Test Cycle is the reference time for relative timings.
Test Vector A Test Vector consists of one signal state line in a test pattern.
It contains:
A period that delimits the beginning and end of the test vector, also called Test Cycle.
Signal states. Each signal state is represented by a symbol, which reflects its level and
direction (input or output mode for bidirectional). See Waveform File Format for more
information about symbols.
Timing data. Each signal has its own timing data. Inputs are stimulated at predefined
times (driven by the hardware of the tester), and outputs are sampled at predefined
Strobe times.
Test Pattern This is a set of test vectors, usually composed of one or two files: one for the signal
states and one for the timing information. They are the results from the conversion
of a simulation. The very first test vector starts at time 0, which is the absolute time
(reference) for the pattern.
© 2021 Microchip Technology Inc.
and its subsidiaries
Manual DS50003170A-page 1
...........continued
Terminology Description
Tset Tset or Timing Set
It is the (named) identification of all timing data for a given test vector. Testers have a
hardware limitation for the maximum number of Tsets in general.
Fset Fset or Format Set
It is the combination of formats of all signals (that is, input mode, output mode or
undriven mode) at a given test vector. The Fsets can change from one test vector to
the next one. However, testers have a hardware limitation for the maximum number of
Fsets. In order to avoid violating the maximum number of Fsets, it is recommended to
carefully check the direction of bidirectional ports in the simulations.
TOS Test Oriented Simulation (TOS)
A specific simulation performed by the designer to build the corresponding test pattern,
which is intended to run on the ATE.
NRZ Non-Return to Zero (NRZ)
Format of a signal which has only a single event transition (at a given time) in a test
vector.
RTZ Return To Zero (RTZ)
Format of a signal, which may have two event transitions, the first to go to HIGH state,
and the second to return to LOW (Zero) state.
RTO Return To One (RTO)
Format of a signal, which may have two event transitions, the first to go to LOW state,
and the second to return to HIGH (One) state.
Advice
Copyright 2021 by Microchip Nantes S.A., printed in France
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means without prior written permission from Microchip Nantes S.A.
DISCLAIMER
The information in this document is subject to change without notice and should not be construed as a commitment of
Microchip Nantes S.A. The reader should, in all cases, consult Microchip Nantes to determine whether any changes
have been made.
NOTICE
This documentation for Microchip Nantes software proprietary product (programs, libraries) is subject to the
conditions of a Software License Agreement, and may be used only by licensees and their employees. Access
to Microchip Nantes documents by other persons is prohibited.
As provided in the Software License Agreement, no copies of the software and documentation may be made, in
whole or part, without express written permission of Microchip Nantes S.A. The license is attached to a "Design
Development", it starts at the "Project Order Entry" date and expires at the "Design Approval" date.
To prevent confusion because of multiple versions and to control unauthorized access and use, all copies of previous
versions of the documentation should be destroyed by the licensee of the product, upon receipt of the latest version.
MICROCHIP NANTES SOFTWARE SUPPORT
Contact the ASIC Field Application Engineer in your local Microchip Technical Center office.
© 2021 Microchip Technology Inc.
and its subsidiaries
Manual DS50003170A-page 2
To ensure accurate and expedient assistance with your questions or problems, please use the hotline call electronic
form.
TRADEMARKS
GATEAID2, OPEN ASIC are trademarks of Microchip Nantes S.A.
CADENCE, MENTOR GRAPHICS, SUN, SYNOPSYS are registered trademarks.
© 2021 Microchip Technology Inc.
and its subsidiaries
Manual DS50003170A-page 3

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: ATMX150RHA

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