Microchip AT697F Handleiding

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Rev. 7703E–AERO–08/11

Rad-Hard 32 bit

SPARC V8

Processor

AT697F

Features

•SPARC V8 High Performance Low-power 32-bit Architecture

–8 Register Windows

•Advanced Architecture:

–On-chip Amba Bus

–5 Stage Pipeline

–32 KB 4-way associative Instruction Cache

–16 KB 2-way associative Data Cache

•On-chip Peripherals:

–Memory Interface

PROM Controller

SRAM Controller

SDRAM Controller

–Timers

Two 32-bit Timers

Watchdog 32-bit Timer

–Two 8-bit UARTs

–Interrupt Controller with 8 External Programmable Inputs

–32 Parallel I/O Interface

–33MHz PCI Interface Compliant with 2.2 PCI Specification

•Integrated 32/64-bit IEEE 754 Floating-point Unit

•Fault Tolerance by Design

–Full Triple Modular Redundancy (TMR)

–EDAC Protection

–Parity Protection

•Debug and Test Facilities

–Debug Support Unit (DSU) for Trace and Debug

–IEEE 1149.1 JTAG Interface

–Four Hardware Watchpoints

•8 and 32-bit boot-PROM Interface Possibilities with EDAC

•Operating range

–Voltages

3.3V ± 0.30V for I/O

1.8V ± 0.15V for Core

–Temperature

-55°C to 125°C

•Clock: 0 MHz up to 100 MHz

•Power consumption: 1 W at 100 MHz

•Performance:

–86 MIPS (Dhrystone 2.1)

–23 MFLOPS (Whetstone)

•Radiation Performance

–Tested up to a total dose of 300 krad (Si) according to the MIL-STD883 method

1019

–SEU error rate better than 1 E-5 error/device/day

–No Single Event Latchup below a LET threshold of 70 MeV.cm

2

/mg

•MCGA-349 (9g) and MQFP-256 packages

•Development Kit Including

–AT697 Evaluation Board

–AT697F Sample

Product specificaties