Microchip SY88073L/83L Handleiding

Microchip Niet gecategoriseerd SY88073L/83L

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SY88 SY88073L/ 083L
Evaluation Board
1G to 12.5G Limiting Post Amplifiers with
Programmable Decision Threshold (073L)
Digital Offset Correction (083L)
Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • San - - http://www.micrel.com
February 26, 2014
Revision 1.0
General Description
The 073L 083LSY88 / evaluation board enables fast and
thorough evaluation of the SY88073L 083L/ limiting
amplifiers.
The board is an easy supply design, driven - - -to use, single
by a high speed pattern generator to a 50- and terminated Ω
scope. The board features simple user adjustability of the
LOS board threshold, through the adjustment of an on-
potentiometer and different setting options selections using
jumpers.
The SY88 are part of Micrel’s industry073L 083L/ -leading
family of ultra small high ptic IC- - -ospeed fiber s.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• - Multi rate operation from 1.0625Gbps to 12.5Gbps
• ) External crosspoint adjustment (073L
• ) Digital offset correction (083L
• Wide differential input range (10mVPP to 1800mVPP)
• -a a Wide SD de ssert or LOS ssert threshold range
− 4.5mVPP to 30mVPP
− 4dB typical electrical hysteresis
• e-a Fast SD assert and LOS d ssert times
− 1µs typical; s m2µ aximum
• Selectable LOS or SD status signal indicator
• − Selectable RXOUT+/RXOUT ( ) polarity 073L
• - - TTL compatible JAM input with internal pull up
• - Low noise CML data inputs with integrated 50Ω
termination impedance to internal reference VREF
• - Low noise CML data outputs with integrated 50Ω
termination impedance
− 30ps typical rise/fall times
• W ± ide range power supply: 3.3V 10%
• − Industrial temp range: 40°C to +85°C
• x Available in a tiny 3mm 3mm QFN package
Applications
• 10G Gigabit Ethernet,
• 8G and 10G Fibre Channel
• SONET OC192; SDH STM64
• WDM/DWDM systems
• OBSAI, CPRI
Markets
• – PON/FTTx XGPON.2 ONU/ONT
• Telecom, datacom/enterprise
• Storage area networks
• - High performance computing
• Wireless
Micrel, Inc.
SY88 /SY88073L 083L Evaluation Board
February 26, 2014
2 Revision 1.0
Ordering Information( )1
Ordering Part Number PCB Revision Description
SY88 SY88073L-EVAL 073L-EB-1-A Evaluation Board for 1.0625G to 12.5G Limiting Post Amplifier with Programmable
Decision Threshold
SY88 SY88083L-EVAL 073L-EB-1-A Evaluation Board for 1.0625G to 12.5G Limiting Post Amplifier with Digital Offset
Correction
Note:
1. 073L 073L 083L The same evaluation board (SY88 - -1-EB A) is used for both SY88 and SY88 .
Evaluation Board
Micrel, Inc.
SY88 /SY88073L 083L Evaluation Board
February 26, 2014
3 Revision 1.0
Evaluation Board Description
The 073LSY88 / 083L evaluation board is designed to
operate with a single 3.3V ±10% power supply and is
configured with AC-coupled inputs and outputs. The high-
speed input and output signals are brought out to SMA
connectors through matched length AC coupled differential -
traces.
AC- Coupled Input
The AC re internally biased as follows:-coupled inputs a
• For the SY88 , the internal 50073L Ωresistors are
terminated to VCC −1.2V. For the SY88083L, the
internal 50Ω resistors are terminated to VCC . −0.9V
AC- Coupled Output
The board is configured with AC coupled outputs to -
interface directly with 50 load equipment inputs. If only Ω
one output is used, the unused complementary output
must be terminated with 50Ω-to-ground.
Coupling Capacitors Selection
The coupling cap value should be carefully selected, acitor
especially when the same circuit is used for multi-rate
applications.
The RC time constant created by the capacitor and the
input termination resistor can cause a baseline DC droop if
the selected capacitor value is too small for the data rate
and the data pattern contains long strings of Consecutive
Identical Digits (CID) cause pattern. It can also -dependent
jitter if the selected value is too large for the data rate.
Choose the coupling cap to get an optimized acitor value
low-frequency cutoff that minimizes the two problems
together.
For 1G/10G or 2.5G/10G application range, 10nF would be
a good choice, but to optimize the coupling be sure
capacitor value for specific application. the
Measurements
Evaluating RXOUT+ and RXOUT−
−
−
−−
1. Set a DC power supply to +3.3V and turn it off.
2. Connect the positive lead to VCC post and the negative
lead to GND post.
3. inp Connect the /EN ut to GND (jumper between pin1
and pin 2 of JP2) to enable the RXOUT+ and RXOUT −
output buffers.
4. 083L For SY88 : Do not install jumpers on JP1 and JP3.
5. 073L For SY88 : Connect VTHN and VTHP to GND
(install jumper on JP1 and jumper between pins 1 and
2 of JP3) to turn off the crosspoint adjustment or
connect VTHN to VTHREF (jumper between pin 2 and
pin 3 of JP3) and apply a voltage to VTHP (JP1 open)
to adjust the eye crossing (start with a voltage close to
VTHREF).
6. Set the desired frequency on a pattern generator with
amplitude between 5mVPP and 1800mVPP. Typical data
patterns are 27 −1 or 223 , −1 PRBS patterns
depending on the application. Because the inputs to
the board are AC-coupled, the voltage offset of the
pattern generator is not sign can be set ificant and
between GND and VCC.
7. Connect the pattern generator with differential outputs
as a data source to the RXIN+ and RXIN inputs on −
the 073L 083LSY88 / evaluation board. Use matched
length differential cables.
8. Turn the power supply on.
9. Obs erve RXOUT+ and RXOUT outputs on a 50− Ω
input scope.
Adjusting Crosspoint (073L)
1. As mentioned in step bove, to adjust crosspoint, 5 a
move the jumper on JP3 to connect VTHN to
VTHREF.
2. Remove the jumper from JP1.
3. Apply a 1.25V DC voltage to TP1 and adjust it slightly
to set crossing at 50%, higher or lower.
Digital Offset Correction (DOC) (083L)
The DOC circuit correct for internal offset and may not be s
able to fully compensate for offset that external circuits
and/or driving devices such TIA may impose at the inputs
of the device.
To enable the DOC function in the SY88 , leave JP1 083L
open or apply a high signal to DOC_EN (pin 2 of JP1).
To disable the DOC function, install a jumper on JP1.
LOS/SD Timing Measurements
The board comes with 10nF coupling cap at the acitors
inputs and outputs. To minimize the effect of the input RC
time constant on the signal delay from the SMA
connectors to the input of the device the caps must be ,
replace with lower values caps (100pF or lower).
Otherwise t increase the measured LOS/SD his delay may
assert/de-assert time . significantly
LOS Hysteresis Measurements
The 073L 083LSY88 / evaluation board provides a
potentiometer (R2) to allow for convenient adjustment of
SD/LOSLVL without the need for an extra power supply.
SD/LOSLVL taps off a potentiometer connected between
VCC and VREF. VREF is an internal reference voltage of
approximately VCC −1.3V. LOSLVLSo, SD/ can be set to
any voltage between VCC Vand CC −1.3V, as specified in
the 073L 083L datasheets. SY88 and SY88

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: SY88073L/83L

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