Microchip MCP41050 Handleiding


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2003 Microchip Technology Inc. DS11195C-page 1
MMCP41XXX/42XXX
Features
256 taps for each potentiometer
Potentiometer values for 10 k, 50 k and
100 k
Single and dual versions
SPI™ serial interface (mode 0,0 and 1,1)
±1 LSB max INL & DNL
Low power CMOS technology
1 µA maximum supply current in static operation
Multiple devices can be daisy-chained together
(MCP42XXX only)
Shutdown feature open circuits of all resistors for
maximum power savings
Hardware shutdown pin available on MCP42XXX
only
Single supply operation (2.7V - 5.5V)
Industrial temperature range: -40°C to +85°C
Extended temperature range: -40°C to +125°C
Block Diagram
Description
The MCP41XXX and MCP42XXX devices are 256-
position, digital potentiometers available in 10 k,
50 k and 100 k resistance versions. The
MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con-
tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con-
sume <1 µA during static operation. A software shut-
down feature is provided that disconnects the “A”
terminal from the resistor stack and simultaneously con-
nects the wiper to the “B” terminal. In addition, the dual
MCP42XXX has a SHDN pin that performs the same
function in hardware. During shutdown mode, the con-
tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS (reset) pin implements a hardware
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan-
nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.
Package Types
16-Bit
Shift
VDD
VSS
SI
SCK
RS SHDN
PB1
PA1
PW1
Resistor
Array 1*
Wiper
Register
PB0
PW0
PA0
Resistor
Array 0
Wiper
Register
Register
S0
Control
Logic
CS
*Potentiometer P1 is only available on the dual
MCP42XXX version.
MCP42XXX
1
2
3
411
12
13
14
8
9
10
5
6
7
PDIP/SOIC/TSSOP
PB1
PA1
PW1
SHDN
SO
RS
PW0
PB0
CS
PA0
SCK
SI
VSS
VDD
MCP41XXX
1
2
3
45
6
7
8
PDIP/SOIC
PB0
PA0
VDD
PW0
VSS
CS
SCK
SI
Single/Dual Digital Potentiometer with SPI Interface
MCP41XXX/42XXX
DS11195C-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS: 10 k VERSION
Electrical Characteristics: Unless otherwise indicated, V DD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for V DD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Rheostat Mode
Nominal Resistance R 8 10 12 kTA = +25°C (Note 1)
Rheostat Differential Non Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco RAB/T 800 — ppm/°C
Wiper Resistance RW 52 100 VDD = 5.5V, IW = 1 mA, code 00h
R
W 73 125 VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current IW-1 +1 mA
Nominal Resistance Match R/R 0.2 1 % MCP42010 only, P0 to P1; T A = +25°C
Potentiometer Divider
Resolution N 8 — Bits
Monotonicity N 8 — Bits
Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3
Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco VW/T 1 ppm/°C Code 80h
Full Scale Error VWFSE -2 -0.7 0 LSB Code FFh, V DD
= 5V, see Figure 2-25
VWFSE -2 -0.7 0 LSB Code FFh, V DD
= 3V, see Figure 2-25
Zero Scale Error VWZSE 0 +0.7 +2 LSB Code 00h, V DD = 5V, see Figure 2-25
VWZSE 0 +0.7 +2 LSB Code 00h, V DD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range VA,B,W 0 — VDD Note 4
Capacitance (CA or CB) 15 pF f = 1 MHz, Code = 80h, see Figure 2-30
Capacitance CW 5.6 pF f = 1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use V DD = 5V)
Bandwidth -3dB BW 1 MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time tS 2 µS V
A = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage e NWB 9 — nV/Hz V
A = Open, Code 80h, f =1 kHz
Crosstalk CT— -95 — dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS , SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation
Schmitt Trigger High-Level Input Voltage V IH 0.7VDD ——V
Schmitt Trigger Low-Level Input Voltage V IL — 0.3VDD V
Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD
Low-Level Output Voltage VOL 0.40 V IOL = 2.1 mA, V
DD = 5V
High-Level Output Voltage V OH VDD
- 0.5 V IOH = -400 µA, VDD = 5V
Input Leakage Current ILI -1 +1 µA CS = V DD, VIN = VSS or VDD, includes VA SHDN=0
Pin Capacitance (All inputs/outputs) C IN
, COUT 10 pF VDD = 5.0V, TA = +25°C, f c = 1 MHz
Power Requirements
Operating Voltage Range V DD 2.7 — 5.5 V
Supply Current, Active IDDA 340 500 µA VDD = 5.5V, CS = VSS , fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static IDDS 0.01 1 µA CS, SHDN, RS = V DD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity PSS 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA
= 4.5V, Code 80h
PSS 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA
= 2.7V, Code 80h
Note 1: VAB
= V
DD , no connection on wiper.
2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I W = 50 µA for
VDD = 3V and IW = 400 µA for VDD = 5V for 10 k version. See Figure 2-26 for test circuit.
3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. V A = V
DD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5: Measured at VW pin where the voltage on the adjacent V W pin is swinging full-scale.
6: Supply current is independent of current through the potentiometers.
2003 Microchip Technology Inc. DS11195C-page 3
MCP41XXX/42XXX
DC CHARACTERISTICS: 50 k VERSION
Electrical Characteristics: Unless otherwise indicated, V DD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for V DD = 5V, VSS = 0V, VB = 0V, T
A = +25°C.
Parameters Sym Min Typ Max Units Conditions
Rheostat Mode
Nominal Resistance R 35 50 65 kTA = +25°C (Note 1)
Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco RAB/T 800 — ppm/°C
Wiper Resistance RW 125 175 VDD = 5.5V, IW = 1 mA, code 00h
R
W 175 250 VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current IW-1 +1 mA
Nominal Resistance Match R/R 0.2 1 % MCP42050 only, P0 to P1;T A = +25°C
Potentiometer Divider
Resolution N 8 — Bits
Monotonicity N 8 — Bits
Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3
Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco VW/T 1 ppm/°C Code 80h
Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, V DD
= 5V, see Figure 2-25
VWFSE -1 -0.35 0 LSB Code FFh, V DD
= 3V, see Figure 2-25
Zero-Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, V DD = 5V, see Figure 2-25
VWZSE 0 +0.35 +1 LSB Code 00h, V DD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range VA,B,W 0 — VDD Note 4
Capacitance (CA or CB) 11 pF f =1 MHz, Code = 80h, see Figure 2-30
Capacitance CW 5.6 pF f =1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use V DD = 5V)
Bandwidth -3dB BW 280 MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time tS 8 µS V
A = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage e NWB 20 — nV/Hz VA = Open, Code 80h, f =1 kHz
Crosstalk CT— -95 — dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS , SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage V IH 0.7VDD ——V
Schmitt Trigger Low-Level Input Voltage V IL — 0.3VDD V
Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD
Low-Level Output Voltage VOL 0.40 V IOL = 2.1 mA, V
DD = 5V
High-Level Output Voltage V OH VDD
- 0.5 V IOH = -400 µA, VDD = 5V
Input Leakage Current ILI -1 +1 µA CS = VDD, VIN = VSS or VDD , includes V
A SHDN=0
Pin Capacitance (All inputs/outputs) C IN
, COUT 10 pF VDD = 5.0V, TA = +25°C, f c = 1 MHz
Power Requirements
Operating Voltage Range V DD 2.7 — 5.5 V
Supply Current, Active IDDA 340 500 µA VDD = 5.5V, CS = VSS , fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static IDDS 0.01 1 µA CS, SHDN, RS = V DD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity PSS 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA
= 4.5V, Code 80h
PSS 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA
= 2.7V, Code 80h
Note 1: VAB
= V
DD , no connection on wiper.
2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I W = VDD/R for
+3V or +5V for 50 k version. See Figure 2-26 for test circuit.
3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. V A = V
DD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5: Measured at VW pin where the voltage on the adjacent V W pin is swinging full scale.
6: Supply current is independent of current through the potentiometers.


Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: MCP41050

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