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User Guide

© 2025 Microchip Technology Inc. and its subsidiaries

DS50003558D - 1

Introducon (Ask a Queson)

The high-speed serial interface block of SmartFusion

®

2 and IGLOO

®

2 FPGA devices, also known as serializer/

de-serializer interface (SERDESIF), supports several serial communication standards. This module integrates

several functional blocks to support multiple high-speed serial protocols in the FPGA. The only dierence

between the SmartFusion 2 and IGLOO 2 SerDes implementations is the means to initialize and congure

the SERDESIF block. In the SmartFusion 2 device, the embedded Arm

®

Cortex

®

-M3 processor within MSS

is used to perform these operations. Whereas, the IGLOO 2 family performs the same function within the

High-Performance Memory Subsystem (HPMS).

This user guide applies to part numbers starting with M2S and M2GL.

Features (Ask a Queson)

The SERDESIF block has the following features:

•PCIe

®

protocol support

•XAUI protocol support

•External Physical Codings Sub-Layer (EPCS) interface supports user dened high serial protocols, such as

Serial Gigabit Media Independent Interface (SGMII) 1000-BaseX and JESD204B protocol support

•Single or multiple serial protocol modes of operation. In multiple serial protocol modes, two protocols can

be implemented on the four physical lanes of the SERDESIF block.

•Arm AMBA

®

APB-3 compliant slave interface for SERDESIF conguration registers access. See https://

www.arm.com/products/amba-open-specications.php.

SmartFusion 2 and IGLOO 2 FPGA High-Speed Serial

Interface User Guide

Product specificaties